Advances in the speed at which data is communicated have progressed in recent years accompanying increases in the amount of data communicated in the field of communication. High-speed transmission data, for example, is generated from low-speed parallel data, using parallel-serial converters. Using setups, holds, etc. by latches, flip flops, etc. driven by clock signals, parallel-serial converters adjust the input timing of data.
Similarly, for example, Japanese Laid-Open Patent Publication No. 2000-196462 recites conversion into a single string of serial data according to a sequence established by a selector driven by a clock signal. Technology is then used that retimes and shapes the waveform of the serial data by sampling the converted serial data by a flip flop that operates based on a clock signal. In this circuit, as the data speed increases, the timing margin for operating latches, flip flops, selectors retiming flip flops, etc. narrows, making the parallel-serial converter susceptible to the effects of fluctuations.
With the conventional technologies above, since accurately detecting phase deviations between converted serial data and the clock signal is difficult, a problem arises in that shaping of the serial data cannot be performed with a high degree of accuracy. For example, if the rising edge of the clock signal deviates from the optimal point of the serial data and the serial data is sampled near the switching point, the serial data that is shaped deteriorates.
As a means of solving the problem above, technology is used that involves forming a replica circuit synchronized with serial data to detect the phase state thereof and executes control such that the phase state of serial data and retiming clock becomes optimal by adjusting the phase based on data obtained from the detection (see, for example, “A Single-40 Gb/s Dual-20 Gb/s Serializer IC with SFI5.2 Interface in 65 nm CMOS”, ISSCC 2009/SESSION 21, [retrieved 2010 Jan. 26] <URL:http://www.techonline.com/learning/techpaper/213403974>).
Nonetheless, with the conventional art above, when the phase state of the replica data above is detected, sampling is performed based on a clock that is the inverse of the retiming clock and since a clock having a cycle of an even multiple of the inverse clock is used for sampling to perform detection, irrespective of the phases not being at the optimal point, detection results indicate a state identical to that for the optimal point (metastable condition) because of the phase relationship between the sampling output for the inverse clock and the clock having the cycle that is an even multiple of the inverse clock.